Please use this identifier to cite or link to this item:
Title: Modeling, simulation and optimization of 14nm high-K/metal gate NMOS with taguchi method
Authors: Mah, S.K. 
Ahmad, I. 
Ker, P.J. 
Tan, K.P. 
Faizah, Z.A.N. 
Issue Date: 2018
Abstract: The developments in electronics technology push the invention of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) towards smaller physical dimension with improvements in both quality and performance. In this paper, design, fabrication and simulation of electrical characteristics of 14nm La2O3/WSi2NMOS is presented. The fabrication and simulation process of device were performed by using Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools, which consists of ATHENA and ATLAS. The designed device was optimized using Taguchi Method that involves orthogonal arrays and analysis of variance (ANOVA). The original results before optimization process for VTHis 0.212648V (7.5% lower than the targeted value) and IOFF is 3.73851×10-9 A/μm while the optimized results for VTH is 0.233321 V (1.44 % higher than the targeted value) and IOFFis 4.732375×10-11 A/Δm which fulfilled the targets based on International Technology Roadmap for Semiconductors (ITRS) 2013. The Taguchi optimization method yields a significantly lower IOFF with an improved ION/IOFF ratio by a factor of 25. © 2018 IEEE.
DOI: 10.1109/SMELEC.2018.8481293
Appears in Collections:UNITEN Scholarly Publication

Show full item record

Google ScholarTM



Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.