Please use this identifier to cite or link to this item:
Title: Scaling down of the 32 nm to 22 nm gate length NMOS transistor
Authors: Afifah Maheran, A.H. 
Menon, P.S. 
Ahmad, I. 
Elgomati, H.A. 
Majlis, B.Y. 
Salehuddin, F. 
Issue Date: 2012
Abstract: In this paper, we provide the downscaling design and simulation of NMOS transistor with 22 nm gate length, based on the 32 nm design simulation from our previous research. A combination Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate instead of SiO2 dielectric from the 32 nm gate length device. The NMOS transistor was simulated using fabrication tool ATHENA and electrical characterization was simulated using ATLAS. The scale down ratio was used and the dimension of device was scaled down with minimal issues. Our simulation shows that the optimal value of threshold voltage (Vth) and leakage currents (Ion and Ioff) was achieved according to specification in ITRS 2011. This provides a benchmark towards the fabrication of 22 nm NMOS in future work. © 2012 IEEE.
Appears in Collections:COE Scholarly Publication

Show full item record

Google ScholarTM


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.