Optimizing 35nm NMOS devices V TH and I LEAK by controlling active area and halo implantation dosage

Abstract

CMOS transistor reaches physical and electrical limitations technology passes through the critical 90 nm gate size. Scaling down linearly to 35nm, the transistor electrical characteristics behave even more unpredictable. This can be seen with leakage current increasing exponentially as the physical size reduced linearly, mainly caused by the short channel effect. As a result, the threshold voltage (V TH) values becoming to low for the transistor to act as a switch. Containing this leakage current under a desired value is crucial for reliable high-speed chip design. Fabricating a 35nm NMOS transistor, ion implantations is one of a main area that determine the amount of the leakage current. A transistor source/drain is created with that implantation. In our experiment, we used arsenic and phosphorus to dope the active area. The initial fabricated NMOS transistor threshold voltage value is way off ITRS predicted value with at around 5V. Sweeping the active area ion implantation dosage and depth would not give us a working transistor as the best V TH obtained is 3.314V, which is still far off the ITRS prediction of 0.12V. As such we also vary the transistor halo ion implantation dosage and power. In theory, halo implantation is supposed to shift the threshold voltage of the transistor and significantly reduce the short channel effect that causes the said leakage current due to dopant channeling through polycrystalline silicon grain boundary. Indium was used as the element for halo implantation with the implanting equipment set to 30 degree tilting and 360 degree rotation around the wafer. Hence, we managed to fabricate a transistor that with a threshold voltage of 0.127V with doping concentration of 8.1210 12 particle per m 2. This shows that the design of halo implantation is the key technology for supressing short channel effect and improving subthreshold-slope, I ON and I OFF, adjusting the V TH. The transistor fabrication process of 35 nm NMOS was simulated by using Silvaco ATHENA module and the resulting electrical characterization was simulated using ATLAS module, Taguchi analysis was applied to our experiment results to minimize the time taken to find the best solution. © 2011 IEEE.