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dc.contributor.authorElgomati, H.A.en_US
dc.contributor.authorMajlis, B.Y.en_US
dc.contributor.authorAhmad, I.en_US
dc.contributor.authorSalehuddin, F.en_US
dc.contributor.authorHamid, F.A.en_US
dc.contributor.authorZaharim, A.en_US
dc.contributor.authorMohamad, T.Z.en_US
dc.contributor.authorApte, P.R.en_US
dc.description.abstractThis paper explains our investigation of the effect on 32 nm PMOS device threshold voltage (VTH) by four process parameters, namely HALO implantation, Source/Drain (S/D) implantation dose, compensation implantations, and silicide annealing time. Taguchi method determines the setting of process parameters in experimental design while analysis of variance (ANOVA) determines the influence of the main process parameters on threshold voltage. The fabrication processes of the transistor were performed by ATHENA fabrication simulator, while the electrical characterization of the device was done by an ATLAS characterization simulator. These two simulators were combined and the results were analyzed by Taguchi's method in order to aid in design and optimizing process parameters. Threshold voltage (Vth) results were used as the evaluation parameters. The results show that the VTH value of -0.10319 V is achieved for a 32 nm PMOS transistor. In conclusion, by utilizing Taguchi's method to analyze the effect of process parameters, we can adjust threshold voltage (VTH) for PMOS to a stable value of -0.10319 V that is well within ITRS prediction for a 32 nm PMOS transistor. © 2011 Academic Journals.
dc.titleStatistical optimization for process parameters to reduce variability of 32 nm PMOS transistor threshold voltageen_US
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