RF substrate noise characterization for CMOS 0.18μm

Abstract

In the submicron technologies, RF noise isolation is becoming increasingly important. In this paper, the investigations of the on-chip RF isolation techniques were carried out. The chosen isolation structures were the Deep Nwell (or triple well isolation) and the P+ Guard Ring. The test structures were designed and fabricated using Silterra CMOS 0.18μm Mixed Signal process. The design parameter investigated was the distance between the isolation ring and the output terminal (Sout) in which the substrate coupling effects with and without deep nwell were characterized. © 2004 IEEE.