Please use this identifier to cite or link to this item: http://dspace.uniten.edu.my/jspui/handle/123456789/5980
DC FieldValueLanguage
dc.contributor.authorFaizah, Z.A.N.
dc.contributor.authorAhmad, I.
dc.contributor.authorKer, P.J.
dc.contributor.authorRoslan, P.S.A.
dc.contributor.authorMaheran, A.H.A.
dc.date.accessioned2017-12-08T07:48:13Z-
dc.date.available2017-12-08T07:48:13Z-
dc.date.issued2015
dc.identifier.urihttp://dspace.uniten.edu.my/jspui/handle/123456789/5980-
dc.description.abstractMetal-Oxide-Semiconductor Field Effect Transistors MOSFETs (MOSFETs) transistor have been scaled tremendously through Moore's Law since 1974 in order to compact transistors in a single chip. Thus, a proper scaling technique is compulsory to minimize the short channel effect (SCE) problems. In this paper, the virtual fabricated design and device's characterization of 14 nm HfO2/WSi2 n-type MOSFET device is presented. The device is scaled based on previous research on 32 nm transistors. The virtual fabrication and simulation of n-type MOSFETs are implemented using Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools named ATHENA and ATLAS. From the simulation, result shows that the optimal value of threshold voltage (VTH), drive current (ION) and leakage current (IOFF) are 0.232291 V, 78.922×10-6 A/um and 77.11×10-9 A/um respectively. These simulation results are believed to be able to create a touchstone towards the optimization and fabrication of 14 nm device's gate length utilizing High-K/Metal Gate n-type MOSFET in impending work. © 2015 IEEE.
dc.titleModeling of 14 nm gate length n-Type MOSFET
item.fulltextNo Fulltext-
item.grantfulltextnone-
Appears in Collections:COE Scholarly Publication
Show simple item record

Google ScholarTM

Check


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.