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|dc.description.abstract||The process parameters are very crucial factor in the development of transistors. There are many process parameters that influenced in the development of the transistors. In this research, we investigate the effects of the process parameters variation on response characteristics such as threshold voltage (VTH) and sub-threshold leakage current (IOFF) in 18nm NMOS device. The technique to identify semiconductor process parameters whose variability would impact most on the device characteristic is realized through the process by using Taguchi robust design method. This paper presents the process parameters that influenced in threshold voltage (VTH) and sub-threshold leakage current (IOFF) which includes the Halo Implantation, Compensation Implantation, Adjustment Threshold voltage Implantation and Source/Drain Implantation. The design, fabrication and characterization of 18nm HfO2/TiSi2 NMOS device is simulated and performed via a tool called Virtual Wafer Fabrication (VWF) Silvaco TCAD Tool known as ATHENA and ATLAS simulators. These two simulators were combined with Taguchi L9 Orthogonal method to aid in the design and the optimization of the process parameters to achieve the optimum average of threshold voltage (VTH) and sub-threshold leakage current, (IOFF) in 18nm device. Results from this research were obtained; where Halo Implantation dose was identified as one of the process parameter that has the strongest effect on the response characteristics. Whereby the Compensation Implantation dose was identified as an adjustment factor to get the nominal values of threshold voltage VTH, and sub-threshold leakage current, IOFF for 18nm NMOS devices equal to 0.302849 volts and 1.9123Ã—10-16 A/Î¼m respectively. The design values are referred to ITRS 2011 prediction. Â© 2015 AIP Publishing LLC.||en_US|
|dc.publisher||American Institute of Physics Inc.||en_US|
|dc.subject||TiSi2-Metal Gate Transistor||en_US|
|dc.title||Influence of process parameters on threshold voltage and leakage current in 18nm NMOS device||en_US|
|dc.type||Conference or Workshop Item||en_US|
|Appears in Collections:||COE Scholarly Publication|
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