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dc.contributor.authorAhmad, W.R.W.
dc.contributor.authorKordesch, A.V.
dc.contributor.authorAhmad, I.
dc.contributor.authorYew, P.T.B.
dc.description.abstractIn this paper we investigated the compressive stress in the channel induced by shallow trench isolation (STI) for different active length (Sa). We simulate both PMOS and NMOS for 130nm gate length with five active lengths (Sa=0.34, 0.5, 0.8, 1.0, 5.0um) by using TCAD simulation and compare to experimental data from wafers fabricated using Silterra's 130nm Technology. When the Sa is decreasing, Sxx stress becomes more compressive for both P- and N- MOS while the Syy component becomes more tensile, causing hole mobility improvement in PMOS and electron mobility degradation in NMOS. When Sa decreases from 5um to 0.34um, the Idsat for NMOS is degraded 6.6% and Idsat for PMOS is increased 6%. This means narrower Sa will increases hole mobility performance in p-channel but degrade the electron mobility in n-channel. These results agree with the experimental data. ©2006 IEEE.
dc.titleTCAD Simulation of STI stress effect on active length for 130nm technology
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