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dc.contributor.authorAhmad, W.R.W.
dc.contributor.authorKordesch, A.V.
dc.contributor.authorAhmad, I.
dc.contributor.authorChew, S.A.
dc.contributor.authorYew, P.T.B.
dc.description.abstractIn this paper we investigate the mechanism of local mechanical stress reduction in CMOS transistors by improving the Inter Layer Dielectric (ILD) process. We changed the Etch Stop Liner (ESL) from single stack silicon nitride (SiN) to dual stack ESL SiN/SiON similar to [1]. We then simulate the stress in 2-D for both n- and p- channel MOSFET, and investigate how an oxynitride (SiON) buffer layer under the SiN ESL can reduce the longitudinal (X) and the lateral (Y) stress in both n- and p- channel thus improving the overall CMOS performance. Our result shows that the dual SiN/SiON layer reduces the stress in the channel length direction (Sxx), perpendicular to channel plane direction (Syy) and channel width direction (Szz). It is known that decreasing the compressive stress in the X direction improves NMOS but degrades PMOS. Our experimental data shows that the additional SiON layer reduces the stress in the channel, hence increases the electron mobility.
dc.titleTCAD simulation of local mechanical stress reduction by use of a compressive silicon nitride/silicon oxynitride etch stop bi-layer for CMOS performance enhancement
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