Please use this identifier to cite or link to this item:
http://dspace.uniten.edu.my/jspui/handle/123456789/5727
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Emilliano | en_US |
dc.contributor.author | Chakrabarty, C.K. | en_US |
dc.contributor.author | Basri, A. | en_US |
dc.contributor.author | Ramasamy, A.K. | en_US |
dc.contributor.author | Ping, L.C. | en_US |
dc.date.accessioned | 2017-12-08T06:45:44Z | - |
dc.date.available | 2017-12-08T06:45:44Z | - |
dc.date.issued | 2010 | - |
dc.description.abstract | Currently, FPGA (Field Programmable Gate Array) technology is being widely used for accelerator control owing to its fast digital processing capability. This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall involve ISE Simulator version 9.2i (Xilinx) and Very high integrated circuit Hardware Description Language (VHDL) programming to evaluate the use of Field Programming Gate Array (FPGA) for the detection and counting of partial discharge signals in underground cable. The impulse signals at the input data have very fast rise time in the range of 1 ns to 2 ns. | en_US |
dc.language.iso | en_US | en_US |
dc.relation.ispartof | Internetworking Indonesia JournalOpen Access Volume 2, Issue 1, March 2010, Pages 29-37 | en_US |
dc.title | FPGA simulation of AD converter by using Giga Hertz speed data acquisition for partial discharge detection | en_US |
dc.type | Article | en_US |
dc.identifier.doi | https://www.scopus.com/record/display.uri?eid=2-s2.0-84865150970&origin=resultslist&sort=plf-f&src=s&sid=7d06adada125e669615f834570c5ec3d&sot | - |
item.grantfulltext | none | - |
item.fulltext | No Fulltext | - |
Appears in Collections: | COE Scholarly Publication |
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