Please use this identifier to cite or link to this item:
http://dspace.uniten.edu.my/jspui/handle/123456789/8827
DC Field | Value | Language |
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dc.contributor.author | Toh, C.L. | |
dc.contributor.author | Norum, L.E. | |
dc.date.accessioned | 2018-02-21T04:32:52Z | - |
dc.date.available | 2018-02-21T04:32:52Z | - |
dc.date.issued | 2016 | |
dc.identifier.uri | http://dspace.uniten.edu.my/jspui/handle/123456789/8827 | - |
dc.description.abstract | Power electronics converters are a key component in high voltage direct current (HVDC) power transmission. The modular multilevel converter (MMC) is one of the latest topologies to be proposed for this application. An MMC generates multilevel output voltage waveforms which reduces the harmonics contents significantly. This paper presents a VHDL implementation of the capacitor voltage balancing control and level-shifted pulse width modulation (LSPWM) for MMC. The objective is to minimize the processing time with minimum gate counts. The design details are fully described and validated experimentally. An experiment is conducted on a small scale MMC prototype with two units of power cells on each arm. The test results are enclosed and discussed. © 2016 Institute of Advanced Engineering and Science. All rights reserved. | |
dc.title | VHDL implementation of capacitor voltage balancing control with level-shifted PWM for modular multilevel converter | |
item.grantfulltext | none | - |
item.fulltext | No Fulltext | - |
Appears in Collections: | COE Scholarly Publication |
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