DSpaceCRIS@UNITENhttp://dspace.uniten.edu.my/jspuiThe DSpace digital repository system captures, stores, indexes, preserves, and distributes digital research material.Sun, 18 Aug 2019 06:48:45 GMT2019-08-18T06:48:45Z50141- Design and optimization of 22 nm gate length high-k/metal gate NMOS transistorhttp://dspace.uniten.edu.my/jspui/handle/123456789/5217Title: Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor
Authors: Afifah Maheran, A.H.; Menon, P.S.; Ahmad, I.; Shaari, S.; Elgomati, H.A.; Salehuddin, F.
Abstract: In this paper, we invented the optimization experiment design of a 22 nm gate length NMOS device which uses a combination of high-k material and metal as the gate which was numerically developed using an industrial-based simulator. The high-k material is Titanium dioxide (TiO2), while the metal gate is Tungsten Silicide (WSix). The design is optimized using the L9 Taguchi method to get the optimum parameter design. There are four process parameters and two noise parameters which were varied for analyzing the effect on the threshold voltage (Vth). The objective of this experiment is to minimize the variance of Vth where Taguchi's nominal-the-best signal-to-noise ratio (S/N Ratio) was used. The best settings of the process parameters were determined using Analysis of Mean (ANOM) and analysis of variance (ANOVA) to reduce the variability of Vth. The results show that the Vth values have least variance and the mean value can be adjusted to 0.306V ±0.027 for the NMOS device which is in line with projections by the ITRS specifications.
Tue, 01 Jan 2013 00:00:00 GMThttp://dspace.uniten.edu.my/jspui/handle/123456789/52172013-01-01T00:00:00Z
- Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi methodhttp://dspace.uniten.edu.my/jspui/handle/123456789/5222Title: Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method
Authors: Elgomati, H.A.; Majlis, B.Y.; Ahmad, I.
Abstract: This paper describes our investigation of the effect of seven processes' parameters on threshold voltage (VTH) in the fabrication of a 32nm CMOS transistor. The parameters are HALO implantation, S/D Implantation, Compensation implantations, SiO2 thickness, VTH adjustment implantation, polysilicon thickness and silicide annealing time. The setting of process parameters were determined by Taguchi method L18 experimental design. From there, the level of importance of each of the process parameters on threshold voltage was determined using analysis of variance (ANOVA). Transistor fabrication was performed by using Silvaco ATHENA module. Silvaco ATLAS module takes care of electrical characterization for the device. These two simulators results were analyzed with Taguchi method to aid in design and optimizing process parameters. Threshold voltage (VTH) results were used as the evaluation parameters. The results show that the VTH value 0.1099 V for NMOS can be achieved respectively, much closer to the ITRS prediction than our previous L9 experiment result. As the conclusion, by utilizing L18 Taguchi Method shown that process parameters can adjust threshold voltage (VTH) to a stable value of 0.1099 V that is well within ITRS 2003 prediction for 32nm transistor © 2012 American Institute of Physics.
Sun, 01 Jan 2012 00:00:00 GMThttp://dspace.uniten.edu.my/jspui/handle/123456789/52222012-01-01T00:00:00Z
- Design and optimization of 22nm NMOS transistorhttp://dspace.uniten.edu.my/jspui/handle/123456789/5228Title: Design and optimization of 22nm NMOS transistor
Authors: Afifah Maheran, A.H.; Menon, P.S.; Ahmad, I.; Shaari, S.; Elgomati, H.A.; Majlis, B.Y.; Salehuddin, F.
Abstract: In this paper, we investigate the effects of four process parameters and two process noise parameters on the threshold voltage (V th) of a 22nm NMOS transistor. We used TiO 2 as the high-k material to replace the SiO 2 dielectric. The NMOS transistor was simulated using the fabrication tool ATHENA and electrical characterization was simulated using ATLAS. Taguchi's experimental design strategy was implemented with the L9 orthogonal array for conducting 36 simulation runs. The simulators were used for computing V th values for each row of the L9 array with 4 combinations of the 2 noise factors. The objective function for minimizing the variance in V th is achieved using Taguchi's nominal-the-best signal-to-noise ratio (SNR). Analysis of Mean (ANOM) was used to determine the best settings for the process parameters whereas. Analysis of variance (ANOVA) was used to reduce the variability of Vth. The best settings were used for verification experiments and the results show V th values with the least variance and that the mean value can be adjusted to 0.306V ±0.027 for the 22nm NMOS, which is well within the ITRS2011 specifications.
Sun, 01 Jan 2012 00:00:00 GMThttp://dspace.uniten.edu.my/jspui/handle/123456789/52282012-01-01T00:00:00Z
- Modelling of process parameters for 32nm PMOS transistor using Taguchi methodhttp://dspace.uniten.edu.my/jspui/handle/123456789/5226Title: Modelling of process parameters for 32nm PMOS transistor using Taguchi method
Authors: Elgomati, H.A.; Majlis, B.Y.; Hamid, A.M.A.; Susthitha, P.M.; Ahmad, I.
Abstract: As CMOS technology scales down to the nanometer level process variation can produce deviation in device parameters which affect circuit performance. In this paper, we investigate the effect of seven process parameters and two process noise parameters on threshold voltage (Vth) in a 32nm PMOS transistor. Using Taguchi's experimental robust design strategy seven process parameters were assigned to 7 columns of the L18 orthogonal array to conduct 18 simulation runs. Fabrication of the 32nm PMOS transistor was simulated by using the fabrication tool ATHENA and electrical characterization was simulated using ATLAS. These simulators were used for computing Vth simulations for each row of the L18 array with 4 combinations of the 2 noise factors. Taguchi's nominal-the-best S/N ratio was used as the objective functions for the minimization of variance in Vth. The best settings of process parameters were determined using Analysis of Mean (ANOM) and Analysis of Variance (ANOVA) for reducing the variability of Vth. The best settings were used for verification simulations and the results showed that the Vth values had the least variance and the mean value could be adjusted to-0.103V +-0.003 for PMOS, which is well within ITRS specifications. © 2012 IEEE.
Sun, 01 Jan 2012 00:00:00 GMThttp://dspace.uniten.edu.my/jspui/handle/123456789/52262012-01-01T00:00:00Z
- Scaling down of the 32 nm to 22 nm gate length NMOS transistorhttp://dspace.uniten.edu.my/jspui/handle/123456789/5224Title: Scaling down of the 32 nm to 22 nm gate length NMOS transistor
Authors: Afifah Maheran, A.H.; Menon, P.S.; Ahmad, I.; Elgomati, H.A.; Majlis, B.Y.; Salehuddin, F.
Abstract: In this paper, we provide the downscaling design and simulation of NMOS transistor with 22 nm gate length, based on the 32 nm design simulation from our previous research. A combination Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate instead of SiO2 dielectric from the 32 nm gate length device. The NMOS transistor was simulated using fabrication tool ATHENA and electrical characterization was simulated using ATLAS. The scale down ratio was used and the dimension of device was scaled down with minimal issues. Our simulation shows that the optimal value of threshold voltage (Vth) and leakage currents (Ion and Ioff) was achieved according to specification in ITRS 2011. This provides a benchmark towards the fabrication of 22 nm NMOS in future work. © 2012 IEEE.
Sun, 01 Jan 2012 00:00:00 GMThttp://dspace.uniten.edu.my/jspui/handle/123456789/52242012-01-01T00:00:00Z
- Optimization of HALO structure effects in 45nm p-type MOSFETs device using taguchi methodhttp://dspace.uniten.edu.my/jspui/handle/123456789/5242Title: Optimization of HALO structure effects in 45nm p-type MOSFETs device using taguchi method
Authors: Salehuddin, F.; Ahmad, I.; Hamid, F.A.; Zaharim, A.; Elgomati, H.A.; Majlis, B.Y.; Apte, P.R.
Abstract: In this study, the Taguchi method was used to optimize the effect of HALO structure or halo implant variations on threshold voltage (VTH) and leakage current (ILeak) in 45nm p-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) device. Besides halo implant dose, the other process parameters which used were Source/Drain (S/D) implant dose, oxide growth temperature and silicide anneal temperature. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimize the process parameters. In this research, the most effective process parameters with respect to VTH and ILeak are halo implant dose (40%) and S/D implant dose (52%) respectively. Whereas the second ranking factor affecting VTH and ILeak are oxide growth temperature (32%) and halo implant dose (34%) respectively. The results show that after optimizations approaches is -0.157V at ILeak=0.195mA/μm.
Sat, 01 Jan 2011 00:00:00 GMThttp://dspace.uniten.edu.my/jspui/handle/123456789/52422011-01-01T00:00:00Z
- Characterization of fabrication process noises for 32nm NMOS deviceshttp://dspace.uniten.edu.my/jspui/handle/123456789/5248Title: Characterization of fabrication process noises for 32nm NMOS devices
Authors: Elgomati, H.A.; Majlis, B.Y.; Ahmad, I.; Ziad, T.
Abstract: This paper describes the effect of fabrication process noises to Sub-nanometer devices, which in this case a 32nm NMOS transistor. This experiment a part of a full Taguchi Method analysis to obtain an optimum fabrication recipe for the said transistor. The two noises introduced in the fabrication is ±1°C variation in sacrificial oxide layer growth by diffusion temperature and also silicide compress annealing temperature. In this project, a working 32 NMOS transistor fabrication is used. By increasing the sacrificial oxide layer diffusion temperature from 900°C to 901°C, the reference 32nm NMOS transistor threshold voltage (VTH) jumps from 0.1181V to 0.1394V, while leakage current drops from 0.111mA/um to 0.109 mA/um. By decreasing the silicide compress temperature from 910°C to 909°C, threshold voltage increase slightly from 0.118053V to 0.118068V, This shows a very different in magnitude of effect from same degree of noise introduce to the fabrication process. © 2010 IEEE.
Fri, 01 Jan 2010 00:00:00 GMThttp://dspace.uniten.edu.my/jspui/handle/123456789/52482010-01-01T00:00:00Z
- Application of Taguchi method in the optimization of process variation for 32nm CMOS technologyhttp://dspace.uniten.edu.my/jspui/handle/123456789/5239Title: Application of Taguchi method in the optimization of process variation for 32nm CMOS technology
Authors: Elgomati, H.A.; Majlis, B.Y.; Ahmad, I.; Salehuddin, F.; Hamid, F.A.; Zaharim, A.; Apte, P.R.
Abstract: In this paper, we investigate the effect of four process parameters namely HALO implantation, compensation implantations, SiO2 thickness and silicide annealing time on threshold voltage (VTH) in complementary metal oxide semiconductor (CMOS) technology. The setting of process parameters were determined by Taguchi method in experimental design. The influence of the main process parameters on threshold voltage were determined using analysis of variance (ANOVA). The fabrication processes of the transistor were performed by a simulator namely ATHENA. The electrical characterization of the device was done by the a simulator of ATLAS. These two simulators were combined with Taguchi method to aid in design and optimizing process parameters. The other two parameter used in this experiments were Source/Drain (S/D) implantation dose and, silicide annealing temperature Threshold voltage (Vth) results were used as the evaluation parameters. The results show that the VTH value of 0.10308V and -0.10319V for NMOS and PMOS respectively. As conclusion, by utilizing Taguchi Method shown that process parameters can adjust threshold voltage (VTH) to a stable value of 0.103V that is well within ITRS prediction for 32nm transistor.
Sat, 01 Jan 2011 00:00:00 GMThttp://dspace.uniten.edu.my/jspui/handle/123456789/52392011-01-01T00:00:00Z
- Statistical optimization for process parameters to reduce variability of 32 nm PMOS transistor threshold voltagehttp://dspace.uniten.edu.my/jspui/handle/123456789/5240Title: Statistical optimization for process parameters to reduce variability of 32 nm PMOS transistor threshold voltage
Authors: Elgomati, H.A.; Majlis, B.Y.; Ahmad, I.; Salehuddin, F.; Hamid, F.A.; Zaharim, A.; Mohamad, T.Z.; Apte, P.R.
Abstract: This paper explains our investigation of the effect on 32 nm PMOS device threshold voltage (VTH) by four process parameters, namely HALO implantation, Source/Drain (S/D) implantation dose, compensation implantations, and silicide annealing time. Taguchi method determines the setting of process parameters in experimental design while analysis of variance (ANOVA) determines the influence of the main process parameters on threshold voltage. The fabrication processes of the transistor were performed by ATHENA fabrication simulator, while the electrical characterization of the device was done by an ATLAS characterization simulator. These two simulators were combined and the results were analyzed by Taguchi's method in order to aid in design and optimizing process parameters. Threshold voltage (Vth) results were used as the evaluation parameters. The results show that the VTH value of -0.10319 V is achieved for a 32 nm PMOS transistor. In conclusion, by utilizing Taguchi's method to analyze the effect of process parameters, we can adjust threshold voltage (VTH) for PMOS to a stable value of -0.10319 V that is well within ITRS prediction for a 32 nm PMOS transistor. © 2011 Academic Journals.
Sat, 01 Jan 2011 00:00:00 GMThttp://dspace.uniten.edu.my/jspui/handle/123456789/52402011-01-01T00:00:00Z
- Control factors optimization on threshold voltage and leakage current in 22 nm NMOS transistor using Taguchi methodhttp://dspace.uniten.edu.my/jspui/handle/123456789/5181Title: Control factors optimization on threshold voltage and leakage current in 22 nm NMOS transistor using Taguchi method
Authors: Afifah Maheran, A.H.; Menon, P.S.; Ahmad, I.; Salehuddin, F.; Mohd, A.S.; Noor, Z.A.; Elgomati, H.A.
Abstract: In this article, Taguchi method was used to optimize the control factor in obtaining the optimal value which is also known as response characteristics, where the threshold voltage (Vth) and leakage current (Ileak) for NMOS transistor with a gate length of 22 nm is taken into account. The NMOS transistor design includes a high permittivity material (high-k) as a dielectric layer and a metal gate which is Titanium Dioxide (TiO2) and Tungsten Silicide (WSiX) respectively. The control factor was optimized in designing the NMOS device using the Taguchi Orthogonal Array Method where the Signal-To-Noise Ratio (SNR) analysis uses the Nominal-The-Best (NTB) SNR for Vth, while for Ileak analysis, a Smaller-The-Better (STB) SNR was used. Four manufacturing control factors and two noise factor are used to optimize the response characteristics and find the best combination of design parameters. The results show that the Halo implantation tilting angle is the dominant factor where it has the greatest factor effect on the SNR of the Ileak with 55.52%. It is also shown that the values of Vth have the least variance and the mean value can be set to 0.289 V ± 12.7% and Ileak is less than 100 nA/μm which is in line with the projections made by the International Technology Roadmap for Semiconductors (ITRS).
Sun, 01 Jan 2017 00:00:00 GMThttp://dspace.uniten.edu.my/jspui/handle/123456789/51812017-01-01T00:00:00Z
- Cobalt silicide and titanium silicide effects on nano deviceshttp://dspace.uniten.edu.my/jspui/handle/123456789/5235Title: Cobalt silicide and titanium silicide effects on nano devices
Authors: Elgomati, H.A.; Majlis, B.Y.; Salehuddin, F.; Ahmad, I.; Zaharim, A.; Hamid, F.A.
Abstract: This paper describes growth process of the two silicide Sub-nanometer devices and the different effects of having cobalt silicide and titanium silicide on a Sub-nanometer CMOS devices. On the top of CMOS device gate, metal silicide is developed on-top of the polysilicon to produce an ohmic contact between the polysilicon and aluminum wire. The ohmic contact should be better compared to metal-polysilicon borders. This silicide has been widely used to reduce resistance of polysilicon gates. Metal silicides such as titanium silicide (TiSi 2), tungsten salicide (WSi 2), cobalt salicide (CoSi 2) andnickel salicide (NiSi 2) are widely used for this purpose. These metals react with polysilicon, to form metal silicide layer that possesses better physical and electrical properties to interface with aluminium. The silicide need to be optimally annealed in order to obtain a good ratio of metal silicide to silicon in the gate structure Titanium silicide is formed by depositing PVD Ti on silicon substrates followed by annealing process. Anneals were carried out in an N2 ambient and resulted in a thin TiN layer on the silicide surface. For cobalt cilicide, a CVD cobalt layer was deposited on-top silicon at 450C, and after annealing the structure, Co 2Si phase was formed. And at 800C the high resistivity CoSi phase formed. As we continued to increase the anneal temperature to 950C, CoSi 2 layer is formed. The high temperature required to form a silicide and the non existence of the Co 2Si phase are attributed to the oxide at the interface. It is found that cobalt silicide grew faster and deeper to the silicon, thus saving a lot of time and cost. The succeding experiments also show that cobalt silicide has better electrical properties such as sheet resistance, capacitance and electron mobility. The transistor fabrication process was simulated by using Silvaco ATHENA module and the resulting electrical characterization was simulated using ATLAS module. © 2011 IEEE.
Sat, 01 Jan 2011 00:00:00 GMThttp://dspace.uniten.edu.my/jspui/handle/123456789/52352011-01-01T00:00:00Z
- Optimizing 35nm NMOS devices V TH and I LEAK by controlling active area and halo implantation dosagehttp://dspace.uniten.edu.my/jspui/handle/123456789/5237Title: Optimizing 35nm NMOS devices V TH and I LEAK by controlling active area and halo implantation dosage
Authors: Elgomati, H.A.; Majlis, B.Y.; Salehuddin, F.; Ahmad, I.; Zaharim, A.; Hamid, F.A.
Abstract: CMOS transistor reaches physical and electrical limitations technology passes through the critical 90 nm gate size. Scaling down linearly to 35nm, the transistor electrical characteristics behave even more unpredictable. This can be seen with leakage current increasing exponentially as the physical size reduced linearly, mainly caused by the short channel effect. As a result, the threshold voltage (V TH) values becoming to low for the transistor to act as a switch. Containing this leakage current under a desired value is crucial for reliable high-speed chip design. Fabricating a 35nm NMOS transistor, ion implantations is one of a main area that determine the amount of the leakage current. A transistor source/drain is created with that implantation. In our experiment, we used arsenic and phosphorus to dope the active area. The initial fabricated NMOS transistor threshold voltage value is way off ITRS predicted value with at around 5V. Sweeping the active area ion implantation dosage and depth would not give us a working transistor as the best V TH obtained is 3.314V, which is still far off the ITRS prediction of 0.12V. As such we also vary the transistor halo ion implantation dosage and power. In theory, halo implantation is supposed to shift the threshold voltage of the transistor and significantly reduce the short channel effect that causes the said leakage current due to dopant channeling through polycrystalline silicon grain boundary. Indium was used as the element for halo implantation with the implanting equipment set to 30 degree tilting and 360 degree rotation around the wafer. Hence, we managed to fabricate a transistor that with a threshold voltage of 0.127V with doping concentration of 8.1210 12 particle per m 2. This shows that the design of halo implantation is the key technology for supressing short channel effect and improving subthreshold-slope, I ON and I OFF, adjusting the V TH. The transistor fabrication process of 35 nm NMOS was simulated by using Silvaco ATHENA module and the resulting electrical characterization was simulated using ATLAS module, Taguchi analysis was applied to our experiment results to minimize the time taken to find the best solution. © 2011 IEEE.
Sat, 01 Jan 2011 00:00:00 GMThttp://dspace.uniten.edu.my/jspui/handle/123456789/52372011-01-01T00:00:00Z
- Optimization of process parameter variation in 45nm p-channel MOSFET using L18 orthogonal arrayhttp://dspace.uniten.edu.my/jspui/handle/123456789/5225Title: Optimization of process parameter variation in 45nm p-channel MOSFET using L18 orthogonal array
Authors: Salehuddin, F.; Ahmad, I.; Hamid, F.A.; Zaharim, A.; Hamid, A.M.A.; Menon, P.S.; Elgomati, H.A.; Majlis, B.Y.; Apte, P.R.
Abstract: In this study, orthogonal array of L18 in Taguchi method was used to optimize the process parameters variance on threshold voltage (V TH) in 45nm p-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device. The signal-to-noise (S/N) ratio and analysis of variance (ANOVA) are employed to study the performance characteristics of the PMOS device. There are eight process parameters (control factors) were varied for 2 and 3 levels to performed 18 experiments. Whereas, the two noise factors were varied for 2 levels to get four readings of VTH for every row of experiment. VTH results were used as the evaluation variable. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with L 18 Orthogonal Array to aid in design and optimize the process parameters. The predicted values of the process parameters were verified successfully with ATHENA and ATLAS's simulator. In PMOS device, VTH implant dose (26%) and compensate implant dose (26%) were the major factors affecting the threshold voltage. While S/D Implant was identified as an adjustment factor in PMOS device. These adjustment factors have been used to get the nominal values of threshold voltage for PMOS device closer to -0.289V. © 2012 IEEE.
Sun, 01 Jan 2012 00:00:00 GMThttp://dspace.uniten.edu.my/jspui/handle/123456789/52252012-01-01T00:00:00Z
- Analyze of input process parameter variation on threshold voltage in 45nm n-channel MOSFEThttp://dspace.uniten.edu.my/jspui/handle/123456789/5236Title: Analyze of input process parameter variation on threshold voltage in 45nm n-channel MOSFET
Authors: Salehuddin, F.; Ahmad, I.; Hamid, F.A.; Zaharim, A.; Elgomati, H.A.; Majlis, B.Y.
Abstract: In this paper, Taguchi method was used to analyze of input process parameters variations on threshold voltage (V TH) in 45nm n-channel Metal Oxide Semiconductor device. The orthogonal array, the signal-to-noise ratio, and analysis of variance are employed to study the performance characteristics of a device. In this paper, there are eight process parameters (control factors) were varied for 2 and 3 levels to performed 18 experiments. Whereas, the two noise factors were varied for 2 levels to get four readings of VTH for every row of experiment. VTH results were used as the evaluation variable. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimize the process parameters. In this research, S/D implant energy was identified as one of the process parameter that has the strongest effect on the response characteristics. While the halo implant dose was identified as an adjustment factor to get the nominal values of VTH for NMOS device equal to 0.289V at tox 1.06nm. © 2011 IEEE.
Sat, 01 Jan 2011 00:00:00 GMThttp://dspace.uniten.edu.my/jspui/handle/123456789/52362011-01-01T00:00:00Z