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Title: Analysis of corner effects of The vertical MOS transistors using 3D device simulation
Authors: Chien Fat Chau
Issue Date: Oct-2003
Abstract: Increasing industry’s demands for greater performance and functionality at lower cost has pushed many foundries to work beyond the visions of Moore’s Law and International Technology Roadmap for Semiconductor (ITRS). In fact, the rate of progress has always been ahead of the predicted features envisioned by ITRS [1.1], [1.2]. This astonishing technological advancement has been historically achieved through the scaling down of the device dimensions, both the vertical dimensions, such as the gate dielectric thickness and junction depth, and the lateral dimensions, such as gate length and lithographic feature size or pitch size. At present, in high performance applications, transistor dimensions have shrunk into nanometer regime, with gate length at sub-lOOnm regime and gate oxide thickness less than 2nm. At this nanometer regime, direct quantum-mechanical tunneling of carriers starts to occur, resulting in an exponential increase in off-state leakage current. In addition, the physical thickness limit of the gate oxide layer, for instance, is predicted to be 7 A in order to properly function as a dielectric layer [1.3], [1.4], Hence, conventional down scaling obviously cannot continue forever. Future improvement, inevitably, needs innovative measures to surmount the barriers of scaling due to fundamental physical constraints. 1.2 Alternative
Description: A dissertation submitted in partial fulfilment of the degree of MSc by examination and dissertation
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